A new data interface for battery management systems has been designed to provide interference immunity and to support distributed battery systems, writes Jon Munson from Linear Technology.
For reliability of battery packs being designed into hybrid electric vehicle drive-trains, an important factor is the electronics employed in the battery management subsystem (BMS).
To date, most pack designs are constrained to single assemblies by the centralised nature of the battery management hardware. In particular, the electrically noisy working environment of the battery and associated equipment places harsh limitations on data communication links that are required to transport vital information within the vehicle.
The ubiquitous CANbus was designed to handle this level of noise-rejection, but the data throughput demands of raw BMS data and component costs associated with it tend to preclude modularization and distribution of cell modules into structurally attractive designs, especially to provide good weight distribution.
Enter the physical layer adaptation of the standard chip-level Serial Peripheral Interface (SPI), we called isoSPI.
How the isoSPI works
To handle high levels of interference, the primary technique to employ is differential signalling on a “balanced” wire pair (neither wire grounded). This permits noise to ride on the wires, but since the noise on both wires (the common-mode) will be nearly identical, the transmitted difference-mode signal remains relatively unaffected.
To handle really large common-mode noise ingress, an isolation method is required as well, the simplest being a magnetic coupling as provided by a tiny transformer. The transformer windings couple the important difference information across the dielectric barrier, but being electrically insulated, does not strongly couple the common-mode noise. These are the same approaches used in Ethernet twisted-pair standards.
The last aspect is to tailor the signalling scheme to provide a full-duplex SPI activity map that supports up to 1Mbit/s signalling yet only requires a single twisted-pair for transmission.
By incorporating all these techniques, isoSPI was designed from the outset to offer error-free transmission while subjected to the rigors of bulk current injection (BCI) interference testing. In practice, full performance against ultra-harsh 200mA BCI has been demonstrated.
A battery management subsystem (BMS) typically involves connecting analogue-to-digital converters (ADCs) to a processor that in turn interfaces to a CANbus link for message interchange within the vehicle.
To achieve complete galvanic isolation for safety and data integrity with the SPI signalling, dedicated data isolator units are required for each ADC unit. These may utilise magnetic, capacitive, or optical means to float the cell-stack from the host microprocessor system and CANbus network, but since they have to handle four signal paths, these are rather expensive components.
With an isoSPI implementation, a transformer is used to provide the galvanic barrier between the host processor elements and the battery pack potential.
At the host microprocessor, a small adapter IC (LTC6820) provides the isoSPI master interface. The ADC units shown (LTC6804-2) include integrated isoSPI slave support so the only additional circuitry required is proper termination resistances that a balanced transmission-line structure requires.
While the figure shows just two ADC units, up to sixteen can be serviced on a single extended isoSPI bus.
The isoSPI links will work fine with simple point-to-point connections, and as shown in Figure 2, dual-port ADC devices (LTC6804-1) can form fully isolated daisy-chain structures. There is a similar overall structural complexity involved in either the bus or daisy-chain approach, so particular aspects of a design may favour one or the other depending on the subtleties involved.
The daisy chain tends to be slightly less expensive, since it needs no address setting feature and generally involves simpler transformer couplings; whereas the parallel addressable bus has better fault-tolerance.
A distributed battery management sub-system
The use of isoSPI networking for ADC information means all the data processing activity can be consolidated into a single microprocessor circuit that need not even be co-located with any of the battery units at all.
Some of the bus is actually resident within a module, but ultimately leaves again to propagate to the next module.
One detail to note is that whenever an isoSPI segment is exposed to harness-level conditions (and thus subject to BCI interference testing), a small common-mode-choke (CMC) is placed in the connections with the associated isoSPI ports on the ICs involved.
The CMC is a very small transformer element that completes the rejection of any residual VHF common-mode noise that may leak through the inter-winding capacitance of the coupling transformer. Additionally, harness wiring is fully isolated for complete safety.
