Texas Instruments has developed an ARM Cortex-M0 that can sleep on zero power and wake in 400ns, intended to run on harvested power.
Key to the chip is ferroelectric RAM (FRAM) non-volatile logic (NVL), where the state of flip-flops is held without power.
"For energy harvesting applications, NVL is a must-have because there is no constant power source available to keep flip-flops alive, and even when the intermittent power source is available, boot-up code alone may consume all of the harvested energy," said TI.
Flip-flop state is held in 256bit mini-arrays of frerroelectric capacitor-based bit-cells dispersed throughout the logic cloud.
"We rejected using a large centralised FRAM array due to the high wake-up time, excessive routing and power costs caused by the lack of parallel access to system flip-flops," said TI.
Specification
Along with the M0 core, the chip has UART and SPI interfaces, 10kbyte ROM, 8kbyte SRAM and 64kbyte FRAM.
The 0.13μm chip runs from a single 1.5V supply, has an 8MHz system clock, and a 125MHz clock for NVL operation.
Consumption is 75μA/MHz and 170μA/MHz, while running code from SRAM and FRAM respectively.
The cost of backing up and restoring the entire system state (2,537 flip-flops) are 4.72nJ/320ns to RAM and 1.34nJ/384ns to FRAM.
Source:
http://www.electronicsweekly.com/Articles/2013/02/22/55619/isscc-cortex-m0-sleeps-on-nothing-and-wakes-in-400ns.htm
