The Phoenix-RTOS has been ported to EnSilica’s eSi-RISC family of soft processor cores providing an embedded RTOS capable of utilising eSi-RISC’s hardware MMU with memory protection and security features such as data execution protection.
It also paves the way for embedded power line and wireless smart grid products using Phoenix proposed smart grid software protocol stacks and eSi-RISC’s support for custom instructions accelerating performance and improving PHY layer implementations.
Additional components, such as TCP/IP and USB stacks, common file systems and POSIX interface, further leverage its potential for machine-to-machine communication and smart grid applications.
EnSilica’s eSi-RISC uses the GNU optimizing C/C++ compiler and Eclipse IDE for software development, and supports debugging on the target through a JTAG interface and hardware breakpoints.
The development suite, which will include Phoenix-RTOS in the next release, is common to both 16-bit and 32-bit processors.
Source:
http://www.electronicsweekly.com/Articles/2013/01/28/55453/phoenix-rtos-ported-to-ensilica-cores.htm
