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Researchers in China and Hong Kong Have Claimed The Highest Output Power Density

Researchers in China and Hong Kong have claimed the highest output power density and power-added efficiency reported to date for gallium nitride (GaN)-based enhancement-mode metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) at 4GHz and in pulsed-mode [Sen Huang et al, IEEE Electron Device Letters, published online 15 June 2015].

Enhancement-mode or 'normally-off' devices are desired for radio frequency (RF), microwave and power applications, giving fail-safe operation and simpler gate control. Unfortunately, without special processing, GaN HEMTs tend to be 'normally-on'/depletion-mode.

Gate recessing and the addition of a gate dielectric can produce enhancement-mode devices with high transconductance and low gate leakage. Gate recessing requires some form of etch, which can introduce lattice damage. Also, the etch process can leave residues. Both these factors can introduce electron trap states that negatively impact performance.

The team from Chinese Academy of Sciences' Institute of Microelectronics, Xidian University, and Hong Kong University of Science and Technology (HKUST) have developed a high-temperature plasma etch that removes residues and recovers lattice damage.

 Figure 1: (a) Schematic device structure of E-mode Al2O3/AlGaN/GaN MISHEMTs. (b) TEM cross-sectional view of gate edge of E-mode MISHEMTs with gate recessed at 180°C.

High-Temperature Recess for Normally-on Gallium Nitride Transistors

The epitaxial material for the device (Figure 1) was grown by metal-organic chemical vapor deposition (MOCVD) on sapphire. The 21nm Al0.25Ga0.75N barrier was grown on a 1nm AlN interface enhancement layer on GaN buffer. The sheet resistance of the AlGaN/GaN heterostructure was 310Ω/square (1980cm2/V-s mobility).

The ohmic source-drain contacts were fabricated with titanium/aluminium/nickel/gold metalization, annealed at 870°C in nitrogen for 50 seconds. Passivation and etch masking was provided by 100nm silicon dioxide from plasma-enhanced chemical vapor deposition (PECVD).

Gate recessing was performed after mesa isolation. The low-RF-power mixed chlorine/boron trichloride inductively coupled plasma (ICP) etch for the gate recessing was performed at 180°C. "The high temperature enables effective desorption of chlorine-based etching residues, e.g. AlCl3, GaCl3, and NCl3," the researchers explain. The recess depth was about 16nm into the AlGaN barrier.

The recessed gate region was covered with 15nm aluminium oxide gate dielectric from a thermal-mode 300°C atomic layer deposition (ALD). The precursors were trimethylaluminium and water/ozone. The water precursor was used for the first 2nm and the ozone for the remaining 13nm. The use of the water precursor avoided oxidation of the AlGaN barrier. A post-deposition anneal was carried out at 500°C for 1 minute in nitrogen.

The gate electrode was nickel/gold with 1μm length, 100μm width, and 1μm overhangs toward the source and drain electrodes. The gate-drain and gate-source separations were 3μm and 2μm, respectively.

Devices produced with the high-temperature (HT) recess process have similar threshold voltages compared with MISHEMTs from room-temperature (RT) recessing. However, the HT-MISHEMTs have smaller hysteresis in double-mode characteristics, suggesting "significant suppression of deep interface/bulk traps". The OFF-state standby power for the HT-MISHEMT was 6x10-8W/mm for 0V gate and 30V drain.

In small-signal RF measurements on the HT-MISHEMT at 10V drain bias and 2.5V gate, the current-gain cut-off (fT) was 7.6GHz and the unit power gain (fmax) came at 27GHz. The maximum values for the RT device were 5.4GHz and 14.9GHz.


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High-Temperature Recess for Normally-on Gallium Nitride Transistors