ISSCC 2013 - 60th Anniversary
Held every year in February in San Francisco, the IEEE's International Solid State Circuits Conference (ISSCC) is the world showcase for innovative circuit design. This is the 60th conference, and year's theme is 60 years of (em)powering the future.
Highlights
Amongst power supply papers, three papers on high-frequency operation stand out, two using on-chip energy storage and the third employing GaN transistors.
An on-chip dc-dc converter delivering 1.2A using only bond wire inductance was the subject of a paper by the Hong Kong University of Science & Technology.
To keep the size of its capacitors to a minimum, a four phase design was implemented, switching at 100MHz.
At this frequency, the parasitic inductance of a bond wire is sufficient for cycle-by-cycle energy storage, allowing the four necessary inductors to fit inside the package.
"Previous works implement inductors either with on-chip spiral metal inductors, which is expensive in terms of chip area, or on-package air-core surface-mount inductors, which is also costly," said the University. "To minimise the cost for extra phases, parasitic bond wire inductor with nH range intrinsic inductance is utilized to implement a four phase converter. Any extra phase requires nothing but a pair of pads and bond wires."
To further save space, large on-chip input and output capacitors are replaced by a single flying capacitor connected from input to output.
"We notice that input voltage naturally comes with a ripple in near-opposite phase of that of output voltage," said the University. "Building a CFLY across input and output is beneficial not only by a sharing effect that increases effective capacitance for both simultaneously, but also by ripple cancellation effect to further reduce the total capacitance significantly."
0.96A/mm2 current density has been measured in the chip without the use of off-chip inductors.
The chip was fabricated by UMC in a 0.13μm process using 0.68nF for CIN, 1.18nF for CFLY and 1.87nF for COUT.
Effective area is 1.25mm2.
Inductors are manually placed aluminium bond wires with tests showing the converter is compatible with inductance from 3nH to 8nH at least.
Over 80% efficiency is observed from 240mA to 1.2A with a 3nH two-in-parallel inductor, and an efficiency of 82.4% is achieved with a ~8nH inductor at 350mA loading current.
Switched-capacitor dc-dc
MIT went the switched-capacitor dc-dc route to achieves >90% efficiency with loads from 130-500µA, using only on-chip capacitors.
"Switched capacitor converters have gained significant interest as a promising candidate for integrated energy conversion solution that eliminates inductors," said MIT. "However, switched capacitor converter efficiency is limited by bottom plate parasitic capacitance."
To make large on-chip inductors with low parasitic capacitance to ground, the researchers built deep trench ferroelectric capacitors.
Again, this is a four-phase design to reduce output ripple, with two capacitors and 10 switches in each phase to allow reconfiguration to four gain settings (1. 0.66, 0.5 and 0.33).
Since gains of 1 and 0.5 need only one capacitor, the switched further allow each single stage to operate as two sub-phased working 180° apart in these modes to further reduce ripple.
The whole chip runs from the input supply without external voltage
sources other a reference.
Clocked at 8.2MHz, peak efficiency is 93% including the control overhead while supplying 500μA at 0.963V, and a peak of 92% while supplying 1mA (both with an off-chip 10nF output capacitor during measurement).
The chip was fabricated in 0.13μm CMOS by Texas Instruments and occupies 600x610μm.
GaN fets for LEDs
TI presented its own paper on power supplies, using a GaN fet as an 11MHz switch to feed 22W into 20 series power LEDs at 90.6% efficiency.
To get this efficiency at the high clock rate, a quasi-resonant zero-voltage switched topology was implemented, with much of the circuit on a single 0.35μm CMOS chip handling 3.3V and 15V.
The buck converter, using the positive rail as a common connection, is formed from LBUCK and CBUCK with LRESO and the fet's output capacitance resonating for zero-voltage switching
To save power, the fet current sense resistor is low (1Ω), and is only used once in every 16 cycles, being shorted out for the other 15 by a low-voltage silicon mosfet.
Magnetics in the design (850nH resonant and 12μH buck) are on new low permeability, low loss cores. "Efforts have been made to minimise inter-winding capacitance and high frequency resistance due to skin effect," said TI.
The converter is operated in bursts of 11MHz (fixed duty cycle) repeated at 67kHz.
Regulation is by varying the 67kHz duty cycle with 5.3μs maximum on-time at full load.
The chip requires external 3V and 8V supplies.
At 110 and 120V, peak efficiencies are 89.5% and 86.7% for 400mA out. Gate driver losses amount to 1-1.7% of input power. Peak efficiency is 90.6% at a power factor of 0.96 at 400mA out (without gate driver losses).
Compared with a version using a silicon mosfet, the GaN fet version has better efficiency by 6.3% at 133V and 9.5% at 157V.
"These improvements can be attributed to the lower RDSon of
the GaN fet," said TI.
Paper 21.4 90.6% Efficient 11MHz 22W LED driver using GaN FETs and burst-mode controller with 0.96 power factor
Paper 21.1 An 82.4% Efficiency package-bond wire-based four-phase fully integrated buck converter with flying capacitor for area reduction
Paper 21.7 A 93% efficiency reconfigurable switched-capacitor dc-dc converter using on-chip ferroelectric capacitors
At ISSCC this year, 209 papers were accepted out of 629 papers submitted:
74 from North America (30 industry, 43 university, 1 institution/lab)
84 from the Far East (33 industry, 50 university, 1 institution/lab) and
51 from Europe (17 industry, 22 university, 12 institution/lab)
