The new co-processors will be in production in 2012
Intel has unveiled the architecture details of Xeon Phi Co-Processor designed for highly parallel technical applications.
Xeon Phi co-processor is based on the Intel Many-Integrated-Core (Intel MIC) architecture.
Built using Intel's latest 22nm 3D Tri-gate transistor technology, new co-processors will be in production in 2012 to support over 50 core, built with a scalable high bandwidth interconnect and memory subsystem.
The Intel MIC Architecture mainly targets highly parallel technical applications in physics, chemistry, biology and financial services.
The company built cores that are smaller than the Intel Xeon processor cores to optimise the architecture for performance/watt of highly parallel HPC workloads.
The cores have been optimised for HPC workloads, while the company has added the L1 data cache to do both a 512b load and a 512b store per cycle to ensure a large L2 TLB, provide a 512KB L2 cache per core, and add a hardware pre-fetcher.
Xeon Phi Co-Processor does not require the workloads to be re-written in a new programming language or require a programmer to handle with a software-managed memory coherency and consistency model.
The processor runs a standard full service OS and Fortran, C, C++ code can be compiled and run on it.
The new coprocessors are available in a PCIe form factor, taking advantage of the new generation of Intel's Xeon family processors and motherboards direct support of PCIe 3.0.
Currently, the Xeon processor is found in 70% of the top 500 supercomputers in the world and the first generation Xeon Phi is complementary to that, being minimised for highly parallel supercomputing tasks.
