SEMATECH (the international research consortium of semiconductor device, equipment, and materials manufacturers) claims that researchers have made significant advances in post-epitaxial-growth backside clean processing that will prepare III-V technology for high-volume manufacturing. The research leading to these accomplishments was conducted at SEMATECH's facilities at the College of Nanoscale Science and Engineering (CNSE) in Albany, NY, USA and presented at SEMATECH's Surface Preparation and Cleaning Conference in Austin, TX in late March.
Following a two-year effort to improve process parameters and validating III-V on 200mm silicon VLSI process flows, technologists have identified the key mechanisms to enable a robust backside cleaning process and made significant progress in reducing the likelihood of process cross-contamination that could impact a high-volume manufacturing line.
Furthermore, SEMATECH has developed systematic experiments to identify the key mechanisms of backside contamination, which were then used to engineer robust backside clean process using standard high-volume manufacturing toolsets. At the same time, researchers assessed the environmental, safety and health (ESH) risks of applying and processing compound semiconductor films on silicon dioxide wafers.
"To drive cost-effective compliance solutions, SEMATECH is developing new testing and analysis methodologies to evaluate ESH impacts of novel materials," says Hsi-An Kwong, SEMATECH's ESH Technology Center program manager. "After conducting a process analysis of III-V manufacturing line, we were able to identify potential ESH risks, including generation of arsine and arsenic compounds, and develop protocols to help mitigate the impact to environment and safety."
Supported by CNSE's conventional Si CMOS processing capabilities, SEMATECH researchers are now working jointly with chipmakers, equipment and materials suppliers and universities on the ESH and contamination challenges of processing III-V materials in a 300mm fab in order to enable safe implementation of III-V technology for high-volume manufacturing.
III-V compound semiconductors are considered valid candidates as building blocks for the implementation of high-performance, low-power logic devices beyond the 10nm technology node, says SEMATECH. But, to be truly competitive, III-V-based technology must be monolithically integrated with silicon in order to benefit from existing Si-based semiconductor processing, it adds. For successful introduction into a silicon manufacturing line, hetero-integrated III-V-on-Si wafers must be processed with a backside clean and capping processes.
"Through the success of our R&D efforts, SEMATECH is developing manufacturable solutions and practical implementation approaches to enable the fabrication of logic devices and systems on chips with diverse and improved functionalities," says Paul Kirsch, director of Front End Processes (FEP) at SEMATECH.
Silicon-based materials have been the basic layers used in manufacturing CMOS transistors for over half a century, but these staple materials (as well as materials derived from silicon such as insulators and contact metals) are reaching their limits, says SEMATECH, as the industry looks to lower power dissipation in CMOS devices and as scaling approaches the physical limits of silicon transistors. SEMATECH's FEP program is exploring innovative materials, new transistor structures and alternative non-volatile memories to address key aspects of system-level performance, power, variability and cost to help accelerate innovation in the continued scaling of logic and memory applications.
"The backside clean step is a key component of successful introduction of III-V material to a 300mm high-volume manufacturing line," says Chris Hobbs, SEMATECH's FEP program manager. "Success at this step is critical to ensure contamination control through subsequent toolsets."
