Toshiba is offering Structured Arrays licensed from BaySand.
They provide, says Toshiba ‘an ASIC alternative to FPGA with lower cost and power consumption - but still at significantly lower implementation and sample/production turn-around time than standard ASICs’.
This is achieved through the customisation of only a small number of metal mask layers on pre-designed and pre-manufactured base wafers with an optimized logic (gate array) and block memory structure.
Minimising the number of metal layers that need to be customised reduces minimum sample delivery time to just five weeks and has a significant advantage on non-recurring engineering (NRE) costs.
The Structured Arrays offer, says Toshiba: ‘Reduced costs, lower power consumption and, if required, higher performance than FPGA alternatives’.
Structured array designs can be developed with verified RTL data from an FPGA and support FPGA compatibility in terms of memory and I/O architecture. In addition, FPGA package and pin layout compatibility supports “drop-in” replacement for FPGA components.
The Structured Arrays use a 65nm process technology and support up to 30m raw logic gates, 20Mbit of SRAM and a maximum of 1200 I/O pins. LVDS and DDR capabilities are available and options for Gigabit high-speed transceivers (up to 6.5Gbps) are being developed. A 40nm line-up is also under development, targeting high-speed transceivers up to 12.5Gbps.
Source:
http://www.electronicsweekly.com/Articles/2013/03/11/55730/toshiba-offers-structured-arrays.htm
