Fudan University in Shanghai has described a 24-core processor chip that uses both packet and circuit switching for high-bandwidth core-to-core communication at low power.
The architecture, described as 'packet-controlled circuit-switched double-layer network-on-chip' provides 11Tbit/s/W communication with every core sending to its neighbour, and 435Gbit/s bandwidth.
From the network view, the two 4x6 networks float one above the other joined vertically at their nodes by the 24 cores.
Source:
http://www.electronicsweekly.com/Articles/2013/03/19/55793/dual-networks-cut-power-on-24-core-multimedia-chip.htm
