Emerging chip technologies that Arm Holdings announced this week, could help to power mobile networks that are being asked to handle more traffic with more fine-tuned controls.
The provider of the dominant architecture for mobile devices announced an interconnect and a memory controller at the Linley Tech Processor Conference in San Jose, California. Both are designed to help makers of networking, computing and storage gear keep up with increasing demands for high performance and low power consumption. Some of the performance gains they deliver could show up on systems shipping in early 2014.
As more smartphones and tablets load mobile networks with data traffic, base stations need to get both more powerful and smaller. So-called small cells allow operators to reuse scarce spectrum multiple times within the broad footprints that up until now have been covered by one large cell tower. At the same time, carriers can now treat different kinds of traffic differently, laying yet another task on their base stations.
Arm’s CoreLink CCN-504 interconnect technology is the glue that will connect the various cores, functions and cache components within a chip and link those to other system components.
It can achieve throughput of 1T bps (bits per second) in real-world conditions, with maximum speed probably hitting 1.5Tbps, according to Arm Senior Product Manager Ian Forsyth. It can be linked to several types of high-speed network technologies, including 40-Gigabit Ethernet, and could be used in wired as well as wireless network gear, he said.
The Arm architecture is best known as the basis of low-power mobile device chips such as Qualcomm’s Snapdragon. But it is also expanding into servers from companies including Dell, and a wide range of networking silicon vendors have also endorsed the architecture, including Texas Instruments and Broadcom, according to Forsyth.
The CCN-504 can scale up from processors with a single core to four clusters of four cores each, according to Arm. That scaling ability means the same architecture can be used for base stations ranging all the way from in-home femtocells to full-size macro base stations, according to David Sonnier, chief architect in the Networking Components Group at LSI, a lead partner of Arm that will get early access to the interconnect. LSI plans to start shipping samples of SOC (system-on-a-chip) processors with the CCN-504 to cellular infrastructure vendors early next year.
Even as the mobile boom demands more performance and features from network gear, base station vendors are seeking higher integration in the same way PC makers have for years, according to Sonnier. The smallest cellular gear, home femtocells, in some cases are based on a single SOC, he said. That kind of integration is likely to move up into bigger pieces of wireless gear.
One advantage of Arm’s new interconnect is that it will be able to connect a wide range of elements that may go into an SOC, including DSPs (digital signal processors) and specialised functions developed by individual network equipment vendors, Sonnier said. Arm plans to license the interconnect, so makers of different components will be able to use interfaces that talk to it, he said. Licensing should make the CCN-504 more attractive to system makers, Sonnier said.
In addition to networks, the new interconnect can also be used in storage and in servers, where Arm sees a particular need for it in distributed data centres designed to serve applications at high speed from sites closer to users, Forsyth said. Arm’s other lead partner for the CCN-504 is server silicon vendor Calxeda.
Arm’s new memory controller, the CoreLink DMC-520, is designed for faster and more efficient access to internal cache and external memory, saving both time and energy, Forsyth said. It can be used in conjunction with the CCN-504 and is expected in the same time frame.
