Paris-based FPGA partitioning software firm Flexras Technologies has released version 3.2 of its Wasga compiler design suite for FPGA-based prototyping.
This new release supports the Xilinx Virtex-7 FPGA and includes new features that accelerate SoC rapid prototyping.
“Collaboration with Xilinx has allowed us to optimize our partitioning flow for next generation SoC implementations based on Virtex-7 All Programmable FPGA-based prototyping systems,” said Hayder Mrabet, CEO of Flexras Technologies.
“With its timing-driven automatic partitioning and high speed Virtex-7 FPGA Advanced Pin Multiplexing (APM) IP for inter-FPGA communications, Wasga Compiler enables very fast prototyping of complex SoCs, achieving efficient results in days, or even hours,” said Mrabet.
The design tool provides automatic generation of XDC pin-planning and timing constraints for Vivado Design Suite, there is logic replication and pruning to optimize connectivity between FPGAs, and modeling of inter-FPGA configurable cables.
The Wasga Compiler Design Suite supports Dini boards, including the DNV7F2A. It is also included in Reflex’s FPP25 offering. Semiconductor companies, using off-the-shelf or in-house custom boards that include Virtex-7 and other FPGAs, are already benefiting from Flexras’ latest development.
Flexras will demonstrate Wasga Compiler for the Virtex-7 FPGA-based systems at DAC, Booth #1324, June 2-5, 2013, Austin,TX, USA.
“The tremendous growth in ASIC SoC complexity is fueling the demand for ever larger FPGAs and multi-chip partitioning tools,” said Kirk Saban, Virtex-7 product line manager at Xilinx.
