Do not get hung up on the need for high functionality ARM processor-based system-on-chip devices,there is still a lot of action in the low and mid-range of the market,writes Douglas Hunter corporate v-p marketing at Lattice Semiconductor
When is a FPGA an SoC?When it integrates a large amount of the functionality an engineer needs and makes their life easier!
The discussion of system-on-chip(SoC)devices often focuses on the high end of the market,e.g.powerful ARM processors embedded as hard cores in cutting edge FPGAs.However,there is still a lot of action in the low and mid-range of the market.
These devices,perhaps not as sexy as high-end SoCs,do contain a high level of integrated functions beyond the core FPGA that make life easier for a broad swath of engineers.
As an example,in the mid-range of the market,hard IP blocks are embedded in some low cost,low power FPGAs to increase system performance.The IP blocks are implemented using dedicated islands of Asic resources within the FPGA.
They can offer up to 10 times the power and cost reduction of similar implementations in other FPGA fabrics.These blocks perform efficient processing of popular communication protocols,such as PCI Express 2.1,10 Gigabit Ethernet MAC,Gigabit Ethernet MAC and Tri-speed Ethernet MAC,as well as Serial Rapid I/O(SRIO)2.1.
These hard IP blocks have been designed and characterised to meet the rigorous data and control plane timing requirements of each protocol.These hard IP blocks provide industry-compliant OSI Layer-2(link layer)functionality for each protocol as well as additional OSI Layer-1 functionality.
The configurable blocks can be customised by embedding proprietary code in the surrounding FPGA logic fabric.
The FPGAs provide a generic application layer interface between the hard IP blocks and the surrounding logic fabric.Designers can also access network control and statistics vectors within the hard IP blocks.
These hard IP blocks are seamlessly integrated with 6G CEI-Compliant SERDES/PCS blocks to offer complete high bandwidth network interfaces.The combination of SERDES/PCS,hard IP and programmable logic fabric is ideal for completing complex serial protocol-based designs with lower cost,power and footprint,while accelerating time to market.That combination qualifies as a SOIC and delivers clear value.
Looking at the low end of the programmable logic market a small SOIC can solve board management problems such as power management,digital housekeeping and glue logic.
Power management devices are particularly pertinent as today's complex circuit boards do require several different power supplies and the sequencing,power up,power down,monitoring and fault reporting do now require sophisticated programmable circuitry.
These board management challenges have both digital and analog facets.On the digital side there are needs such as reset distribution,LED control,input switching,delays,load control,system management bus interfaces,and memory interfaces.
The analogue side of the power management problem includes functions such as hot swap control,power supply OR'ing,supply sequencing,voltage and current monitoring/measurement,reset generation,as well as DC-DC supply trimming and margining.All of which can be solved through integration and programmability.
Integrating FPGA,CPLD,and analogue functionality into a single package simplifies board management design,reduces the cost of these support functions compared to traditional approaches,improves system reliability and provides a high degree of design flexibility that minimises the risk of circuit board re-spins.
Again,as with mid-range SoCs,it is not as sexy as large ARM processors embedded in a high end FPGA,but the integration can make life easier for engineers in the broad market.
