ARM and Cadence have produced the first in a series of combined products for ARM’s POPs (processor optimisation packs).
POPs have core-hardening acceleration technologies from ARM’s physical IP division.
In the Cadence/ARM product, the POP is tightly coupled to Cadence Encounter RTL-to-GDSII technologies, including RTL Compiler-Physical and the clock concurrent optimisation (CCOpt) design technology.
ARM works closely with the Cadence R&D and Design Services organisations prior to the introduction of new POPs.
Extending to TSMC 28HPM, the ARM-Cadence collaboration includes single, dual and quad-core implementations of Cortex-A9 and Cortex-A15 processors.
POPs contain three things: Artisan physical IP standard cell logic and memory cache instances that are specifically tuned for a given ARM processor and foundry technology; benchmarking to document the conditions and results ARM achieved for the processor implementation across an envelope of configuration and design targets; and thirdly, implementation knowledge including floor plans, scripts, design utilities and a POP Implementation Guide.
The Cadence Encounter RTL-to-GDSII flow includes Encounter RTL Compiler, Encounter Digital Implementation System, and signoff-proven Cadence QRC Extraction, and Encounter Timing System. In addition, the CCOpt technology unifies clock tree synthesis with logic/physical optimisation resulting in significant power, performance and area improvements.
