Swiss researchers have worked with IBM to design a very high speed data converter which will operate at speeds up to 100Gbit/s.
IBM Research has worked with Ecole Polytechnique Fédérale de Lausanne (EPFL) in Switzerland on the design of a prototype analogue-to-digital converter (ADC) fabbed on a 32nm silicon-on-insulator CMOS process with a tiny core area of 22×70 μm2.
The ADC has 8-bit resolution and operates at 100Gbit/s from a single 1V supply, with a total power consumption of 3.1mW.
"This is IBM’s first attempt at designing a new ADC that leverages a standard CMOS logic process, not only resulting in the most efficient ADC in its class, but also opening the possibility to add massive computation power for signal analysis on the same chip with the ADC," said Dr. Martin Schmatz, Systems department manager at IBM Research.
"The new ADC design has several key advantages over similar designs proposed earlier: in terms of speed, power dissipation, and silicon area" says Professor Yusuf Leblebici, director of the Microelectronic Systems Laboratory.
"It is a perfect example of successful industry-university cooperation, having produced world-class results."
The research was presented at the International Solid-State Circuits Conference (ISSCC) in February.
