Belgian lab IMEC was founded on semiconductor process research,and has grown into one of the two organisations in the world that companies partner with for advanced process research.The other is IBM.
TSMC partners IMEC for advanced CMOS,as does Samsung,and almost everyone else.Notable exceptions are Intel,which does its own thing(but does partner IMEC for exa-scale computing),and STMicroelectronics,which only goes to IBM.
Looking into its crystal ball,how does IMEC see the semiconductor industry maintaining Moore's Law and continuing to shrink transistors?
"For 28 and 32nm,the high-k metal gate process is sufficient,"said lab CEO Luc Van den hove."For 22-14nm,channels need to be fully-depleted and it is clear that finfets are the way to go."
Beyond the 14nm node,transistors will get slower if nothing is done to increase the mobility of carriers in the channel region of mosfets.
"Finfets will certainly be extended to the 14nm node,"said Van den hove."Beyond will use high-k dielectric,finfets,and added high-mobility."
To get the mobility,the lab proposes to avoid silicon channels all-together,and instead grow tiny islands of other semiconductors to form the finfet channels(see diagram).
"Ge for p-channel transistors and III-V for the n-channel transistors will bring us beyond 10nm,to 7nm at least,"said Van den hove.
InGaAs is currently favoured for the n-channel,grown on a series of buffer layers to match it with the underlying silicon lattice.
Beyond 7nm,things are getting too small for conventional conduction mechanisms to work effectively and IMEC is looking into quantum tunnelling as an alternative.
"For 7-5nm,we are exploring tunnel FETs,either as finfets or vertical transistors,"said Van den hove.
Vertical FETs have channels in the form of a thin vertical column,passing through an encircling metal gate,allowing the gate field to be applied to the channel from all directions rather than three sides with finfets.
Devices with sub-5nm features are a long way in the future,but still being investigated.
"Graphene is certainly the material beyond 5nm,"said Van den hove.
Conventional 193nm lithography is likely to have run out of steam well before 5nm.
At 20nm,no amount of tricks on a single mask will be sufficient and two mask'double patterning'will be necessary,said IMEC.
Interference patterns from the two masks,applied sequentially,form a sharpened image on the etch resist,allowing smaller features to be formed.
For the patterns to form properly,wafer positioning for the two masks of a double patterning step is even more critical,and therefore costly,than that between masks for different layers,masks are expensive,and double pattering may be needed for two layers on 20nm chips.
If only straight lines are required-for memory for example-'spacer double patterning'and'directed self-assembly'are two single mask techniques that can yield fine structures.
By 14nm,said IMEC,triple patterning will be required-six masks for the two steps rather than the usual two.
This has lead the lab to predict that 13.5nm EUV(extreme ultra-violet)will be cheaper than 193nm triple patterning for the 14nm node,providing the move to 14nm goes along with the introduction of 450mm wafers.
IMEC already has an pre-production EUV lithography tool from Dutch equipment maker ASML(another world leader,only 100km from IMEC)which has processed some 3,000 300mm wafers since it was installed in 2011.And IMEC is about to build a pilot line for 450mm wafer processing.
Handling 450mm wafers with the necessary precision is a major headache,but nothing to the complexity of EUV lithography,with its reflective masks and exotic 13.5nm sources.So much so that Intel has put cash into ASML to assist development.
The source is proving particularly difficult,with the one at IMEC producing 7-15W of energy when 200-500W will be needed for production.
A shift to 13.5nm lithography would fix one thing:chip making has been quietly slipping off the line predicted by Moore's Law,with the features on"28nm"chips actually coarser than 28nm.EUV would put lithography back on Moore's track.
Source:
http://www.electronicsweekly.com/Articles/2012/10/10/54745/imec-scaling-beyond-15nm.htm
