POET Technologies Inc of Toronto, Canada – which, through subsidiary OPEL Defense Integrated Systems (ODIS Inc) of Storrs, CT, USA, has developed the proprietary planar-optoelectronic technology (POET) platform for monolithic fabrication of integrated III-V-based electronic and optical devices on a single semiconductor wafer – has announced completion of the work of its Special Strategic Committee (SSC) and the update of its published milestones. The board of directors has endorsed the firm's commercialization plan put forward by the SSC, which is chaired by executive director Peter Copetti.
The SSC was established last June to investigate and initiate strategic alternatives for the commercialization of the POET technology platform using a multi-faceted approach based on discussions with potential industry partners. The following major recommendations of the SCC have been implemented:
A plan for establishing POET Development Alliances (PDAs) – The firm is in discussion with several potential industry partners who have the necessary foundry infrastructure to take the POET technology to the manufacturing stage. The partnership roles encompass fab, tool and engineering resources as well as product and library development for future applications. Ideal partners will be producers of products that can incorporate the POET IP technology to provide the lowest power consumption and cost-effective industry-disruptive system solutions. Update to Milestone 5 and Milestone 7 – Both milestones are now expected to be completed in the first 3-5 weeks of 2014. Significant progress has been made and both milestones are in the final phases of testing, says the firm. Specific announcements will be made once the final testing is complete for both the Switching Laser Demonstration and the Optical Thyristor-based Infrared Detector and transistor combinations. Drive for reduction of feature size to 100nm range (100nm), Milestone 8 – The firm has introduced new specific milestones associated with reducing feature size to the 100nm range in scale. The POET team has realized submicron device operation down to 200nm. The path to maintaining scaled operation down to 100nm has been identified. The firm has scheduled its molecular beam epitaxy (MBE) system to be shut down for cleaning and maintenance for a period of about 6 weeks after completing Milestones 5 and 7. After restarting MBE, the firm expects to complete Milestone 8 and, accordingly, the timeline for completion of this milestone has been moved to first-quarter 2014. The 100nm goal is matched to the commercial III-V foundry capabilities and will demonstrate the greater than 50x speed improvement together with lower power consumption by a factor ranging from 4 to 10 (depending on the application) compared to silicon at smaller nodes. Significant progress has been made on the completion of this milestone, although it has proven to be more difficult to achieve with the limited equipment available to POET. This highlights the importance of developing an alliance with a fab partner where repeating this milestone and improving it will be significantly easier with advanced lithography equipment standard for CMOS processing, believes the firm.
The firm expects the features of POET (monolithic integration of fully complementary transistors together with optical transmitters and transceivers) to disrupt current optical-electrical techniques with faster and less expensive monolithic IC solutions.
For the first time, it is claimed, p-channel and n-channel devices can be integrated monolithically in a III-V semiconductor environment with the potential to fully replace all silicon based CMOS circuitry with higher speed and lower power. Fully integrated single-device optical transceivers (including the full range of digital data processing at speeds of 100Gbps and beyond) will become a reality, as they cannot be manufactured with current silicon technology for power, speed and cost reasons, the firm adds.
Design kit preparation – In addition to optimizing device parameters and yields, the next focus is to establish POET's technology design kits, a comprehensive design rules and device parameter library for POET enabling customers and partners to implement the POET process into their preferred foundries. It also aims to help licensed designs in a POET device ecosystem to proliferate and help existing silicon library functions to migrate to POET technology-based circuitry in a minimum amount of time. In order for the POET team to focus on the preparation of technology design kits, the SCC has recommended that Milestones 9 and 10 are delayed. New completion dates for those milestones will be announced once a primary industry partner has been identified. Operation management and program management – In addition to appointing a senior VP of operations in November, key management changes are underway at the research facility in Storrs. Efficient program management will be instituted and all documentation and design kit efforts will be handled on-site in a direct manner. This step underscores the current transition from research to development-oriented activities within POET, indicating the maturity of the technology at the present time, says the firm. This management reporting structure should encourage success in finalizating the research stage of POET and provide for the long-term substantiation and transfer of the involved IP, believes the firm. A new development team will be formed with partners to scale the POET technology, bringing it to a mature stage. Globalization plans – The firm is planning several initiatives to raise global awareness of POET and to increase its global investor base. It intends to split monetization of the IP between multiple commercial markets and military applications and products to maximize returns of all the different aspects of the POET IP.
"The SSC's recommendations are the cornerstones of the company's strategy for unlocking the value of POET's intellectual property," says Copetti. "Preparing for a development alliance with comprehensive documentation and full availability of a technology design kit will definitively enable industry partners to incorporate POET technology into their products, thereby shortening time-to-market for potential products, and helping to commercialize POET in the marketplace quickly," he believes. "We are encouraged by our ongoing discussions to date with potential partners. As the general basic strategic goals recommended by the SSC have been adopted by the board of directors, the SSC will be dissolved and the company will now change its focus from research to development, with a view to 2014 being the major recognition year for the POET technology."
The proprietary POET platform has demonstrated planar monolithic standard CMOS fabrication of gallium arsenide (GaAs)-based integrated circuit devices containing both electronic and optical elements on a single wafer. The firm says that, by offering process IP with the potential for increased speed, density, reliability, lower power and costs, POET offers the ability to disrupt Moore's Law to the next level, overcoming current silicon-based lithography and device bottlenecks in regards to speed and power.
The firm is offering a broad technology basis for several key markets. The development of technology design kits in 2014 will focus on a phased approach. Specific markets and partners will be targeted over time as technology design kits become available.
