MIPS is taking ARM's Cortex-A series and Cortex-M4 head-on with three microprocessor cores:proAptive,interAptive and microAptive.
"We have done a large amount of development across our entire portfolio,"MIPS product director Mark Throndson told Electronics Weekly."These are new products,not a re-naming of existing products."
While the fundamental architecture remains the same,changes in performance and features come from different micro architectures.
ProAptive is a step-up from the firm's existing 1074K and 74K series.It is a fused triple-dispatch single-thread superscalar core with out-of-order execution,extended virtual addressing(EVA)and a core-speed floating point unit.
Up to six cores can be used for multi-processing.
Benchmarks for proAptive,which MIPS is pitching against ARM's high-end Cortex-A15,are 4.4CoreMark/MHz and 3.5Dmips/MHz(from FPGA evaluations)-compared with its existing 1074K at 2.8CoreMark/MHz and 2.0dmips/MHz.
Applications are expected in smartphones,3G/4G cellular infrastructure,car multimedia systems and high-end digital TV.
InterAptive is an upgrade to MIPS'existing 24K,34K and 1004K cores with multi-threading,EVA,and one to four cores on a chip.
Intended as a processor for low-and mid-range phone,digital cameras,femtocells and automotive systems(collision avoidance,power train),the firm is setting it against ARM's Cortex-A5 and A7-not the hard-real-time Cortex-R series.
Benchmarks are 3.2CoreMark/MHz and around 1.7Dmips/MHz.
MicroAptive effectively supersedes MIPS'M14K as a control processor.
It has DSP extensions in hardware and is being pitched against the Cortex-M4 which is ARM's M3 general purpose control processor plus DSP extensions.
3.1CoreMark/MHz and 1.57Dmips/MHz are claimed,and applications are expected in touch screens,smart meters,and automotive chassis.
ProAptive
"ProAptive offers 60-75%increased performance compared with our previous high end product line,1074K,"said Throndson."Roughly speaking,proAptive is 50%larger than the 1075K."
And the power consumption?"We are not commenting on power numbers,"said Throndson.
The core intellectual property is fully synthesisable,with a dual-core proAptive plus 1Mbyte of RAM expected to yield around 7,000Dmips.
A clock speed of 1.1GHz is the target on TSMC's 40nm process,1.15GHz from its 28HPM,and a maximum of 2GHz on 28nm HP-dropping slightly if more than four cores are implemented.
"It is designed to run higher than 1GHz,"said Throndson."28HPM is product-ideal,we do have customers interested in 40nm."
There is a 13 stage pipeline,compared to 14 in 1074K,and a new coherency manager.
At an unsustainable peak,four fixed and two floating point instructions can be issued simultaneously.
Half,single and double precision is available from the floating point unit.
Compared with the 1074K,according to Throndson,there is eight times more branch prediction through the branch target buffer and the size of history table.
"For any adjacent instruction in a queue,we can put through both in a single cycle and get up to 2x improvement compared with traditional load-store,"he said."This is much better in real estate than multiple load-store units."
The 2nd-generation(for MIPS)coherency manager now includes the L2 cache controller,runs at the CPU clock speed,and is claimed to halve latency compared to the first generation.
"Typical system latency reduction is from around 24 cycles to 11 cycles,"claimed the firm.
L2 cache sizes from 256kbyte to 8Mbyte are available,and there is configurable access timing for trading-off performance,cost and power.
There are also up to 256 system interrupts,up to two I/O coherence units,and a power controller that can separately set voltage,clock frequency and gate-off each core.
interAptive
InterAptive is a core with hardware multi-threading for two threads,allowing the operating system to map up to nine thread contexts across the hardware pair.
At 1GHz,the firm is claiming 3,350CoreMark/core and 1,750Dmips/core,with up to four cores maximum.
Networking,for example,said MIPS,could require a 1.5GHz quad core,or a phone might need single or dual 500MHz-1GHz cores.
For multi-core operation,the same second-generation coherency manager is offered.
Virtual addressing allows the 32bit address map to reach over 3Gbyte of user space,said MIPS.
Power metrics are once again not being discussed.
To cut power,core clocks can be shutdown during outstanding bus requests and there has been work in L1 instruction and data caches including enabling 32bit accesses of the data cache.
Single error correct,double error detect error correction,already available on the L2 cache in earlier cores,has been extended to L1 cache and scratchpad RAM."This is of a lot of interest for storage,networks and automotive,"said Throndson.
Like proAptive,there are up to 256 system interrupts.
microAptive
MicroAptive is a superset of the M14K/c and comes in two versions,a cache-less microcontroller(MCU)version with a controller and memory protection for the on-board SRAM(diagram),and a microprocessor(MPU)version with cache and a memory management unit(MMU).
The pipeline has five stages and the instruction set is microMIPS,a compressed format analogous to ARM's Thumb-2 set.
For signal processing there are DSP hardware extensions and an enhanced multiply/divide unit.
The dedicated DSP pipeline offers a 8/16bit SIMD engine,159 DSP instructions,70 SIMD instructions,38 Multiply/MAC instructions,single cycle throughput,and supports up to four accumulators.
Compared with M14K which has no DSP extensions,microAptive will execute a FIR16(K=32)four times faster,according to MIPS,knock 20%of the execution time of a FFT32,256(40%off FFT16,256),and is more than twice as fast for H.264_IQT.
Interrupt latency is 10 cycles.
The firm is prediction 400MHz operation on a 65nm LP process,delivering 628Dmips or 1236CoreMark.
In the case of microAptive,MIPS is not so reticent about power.
On a 90nm low-power process,MIPS is expecting 235MHz operation from the microcontroller version with 0.42mm2 footprint and 0.16mW/MHz active power.
This increases to 380MHz on 65nm LP,in 0.24mm2 for 80μW/MHz
On a 65nm'G'process,500MHz is expected from the microprocessor version,in 0.33mm2 and for 100μW/MHz.MicroAptive is available now,with pro and interAptive generally available in the summer.
"We have several licensees of the Aptive generation already,"said Throndson.
Last week,Google announced that Release 8 of the Android Native Development Kit(NDK),with support for the MIPS architecture.
"Today,most Android applications are completely portable and available for MIPS-Based Android devices,"said MIPS."However,a small percentage of applications still benefit from native code for performance reasons.Release 8 includes the required tools,system headers,libraries and debugging support for MIPS."
