APS5 can be implemented in dual-or quad-core configurations
The 32 bit processor IP manufacturer, Cortus has introduced a new high performance, high throughput 32-bit processor designed for complex embedded systems.
APS5 combines good integer computational performance with a high maximum clock frequency and it can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3R.
The performance of the new IP processor can be increased with symmetric multi-processing (SMP) configurations such as dual- or quad-core.
The new 32-bit processor is supplied with an instruction cache and a data cache is optional. Its easy software development, programming in high level languages, with simple debugging architecture enhances both time to market and software reliability.
The APS5 CPU comes with core silicon footprint of 0.088 mm2 in 90 nm (UMC) along with a freely available complete toolchain and IDE.
It interfaces to all of Cortus' peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus as well as bridges to and from AHB-Lite and to APB, ensuring easy interfacing to other IP.
