ARM and Cadence have announced the first Cortex-A57 processor test chip fabricated on TSMC’s 16nm finfet manufacturing process technology.
According to the companies, this test chip resulted in several optimisations between manufacturing process, design IP, and design tools, which will be critical for production of 16nm chips.
“More than ever, success at the leading edge of innovation requires deep collaboration. When designing SoCs incorporating advanced processors, like the Cortex-A57, and optimizing the implementation using physical IP created for FinFET processes, the expertise of our partners is needed,” said Tom Cronk, general manager, processor division at ARM.
The 16nm process using finfet technology required new design methodologies. For example, the design flow tackled RC extraction for 3D transistors, complex resistance models for interconnect and vias, quantised cell libraries and double patterning across more layers.
The test chip was implemented using the complete Cadence RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan standard cell libraries and TSMC’s memory macros.
“This major milestone was challenging on all fronts, requiring engineers from ARM, Cadence and TSMC to work as a unified team,” said Dr. Chi-Ping Hsu, senior vice president of R&D for the Silicon Realization Group at Cadence.
