IBM and Orace reveal their new RISC chips
IBM and Oracle unveiled their respective Power7+ and T5 RISC chips for servers at Hot Chips 2012 symposium in the US.
Expected to be released by the end of 2012, IBM's new, eight-core Power7+, is being manufactured on a 32nm process.
According to IBM, the process allows smaller transistors to equip several new features on the chip with n changes in size and has used some extra space to expand the Level 3 cache memory from 32MB to 80MB on the Power7.
IBM's Scott Taylor said this memory increase will lead to a major performance growth path for scale-up enterprise workloads.
"The Power7+ has 2.1 billion transistors altogether, and it would have had 5.4 billion if IBM had used SRAM," Taylor said.
Additional operations of Power7+ include accelerator units which will accelerate data encryption and other security tasks, a dual chip module that enables clients to incorporate two processors in one socket.
Oracle's upcoming T5 processor is a 28nm shrink of the T4 which was unveiled at the previous year's Hot Chips.
According to Oracle, the T5 have 16 cores, with each operating at up to 3.6GHz, over the 3GHz on the T4.
Oracle's Sebastian Turullols said that one of Oracle's goals for the T5 was to put the chips in as many as eight sockets per server with close to linear scaling.
"There are eight-socket systems you can buy that deliver the equivalent of perhaps only five single sockets," Turullols said.
Features of the new T5 chip include Sparc SuperCluster, which would speed up clustering, which is important for the big machines, along with accelerator units for the 16 encryption algorithms and a random number generator.
