Cadence is working with foundry TSMC on a tool chain and process for 3D chip designs.
3D chip design incorporates multi-chip packages and even multi-die devices with through silicon via(TSV)interconnect technologies.This requires that the design tools must support co-design,analysis and verification of heterogeneous chips and silicon carriers.
TSMC and Cadence have worked together on a tool chain and silicon intellectual property(IP)which has been used in the test-chip tapeout of TSMC's first heterogeneous CoWoS(Chip-on-Wafer-on-Substrate)vehicle."In 2012 3D-IC became a viable option for real-world chip design,"said John Murphy,group director,strategic alliances at Cadence."Big leaps in electronic design don't happen without strong collaboration,and our partnership with Cadence in CoWoS design is a good example,"said Suk Lee,TSMC senior director,design infrastructure marketing division.The tool chain was used to implement multi-chip co-design between digital,custom and package environments incorporating through-silicon vias(TSVs)on both chips and silicon carriers.
It includes key 3D-IC design IP,such as a Wide IO controller and PHY to support Wide IO memories.Test modules were created using the Cadence Encounter RTL-to-GDSII flow,Virtuoso custom/analogue flow,and Allegro system-in-package solutions.
"For 3D-IC design ecosystem readiness,Cadence played an important role in the development of design technology and the necessary IP,"said Lee.
